Silicon-on-insulator (SOI) substrates have been explored as an alternative to other substrates commonly used in fabricating integrated circuit structures. Devices fabricated on SOI substrates demonstrate improved characteristics in very large scale integration circuits (VLSI). SOI devices limit parasitic current since they are built on a buried oxide layer and are completely enclosed by a protective insulating layer, thereby isolating the active device region from the substrate. As a result, parasitic current is prevented from flowing between adjacent transistors sharing a common substrate. SOI devices also have the benefit of reduced capacitance between the source and drain and the semiconductor body resulting in improved transistor performance.
SOI devices have many other advantages over bulk CMOS technology such as higher speeds, higher density, lower power consumption, reduced soft-error rate, and immunity of irradiation. Cheng et al., Improved Hot-Carrier Reliability of SOI Transistors by Deuteriumn Passivation of Defects at Oxide/Silicon Interfaces, IEEE Transactions on Electron Devices, Vol. 49., No. 3, March 2002, pgs. 529-531. For instance, SOI devices have lower power consumption because the underside of the crystalline silicon layer has an insulation layer to prevent current leakage. Further, the threshold voltage is lower because the crystalline silicon layer is very thin.
SOI devices are largely differentiated based on their operating state. Particularly, two kinds of operating states can exist for an SOI device: a partially-depleted or a fully-depleted state. A fully-depleted SOI structure has source/drain diffusion regions which extend completely through the thin silicon layer to the insulator layer. Typically, a fully-depleted SOI device has a very thin crystalline silicon layer disposed above the insulating layer.
Conversely, the diffusion regions in a partially-depleted SOI structure extends only partially into or through the thickness of the silicon layer and does not fully extend to the insulator layer as in a fully-depleted SOI device. Typically, the silicon layer is thicker in a partially-depleted SOI structure. As a result, in comparison to a partially-depleted SOI structure, a fully-depleted SOI structure has lower power consumption and threshold voltage. However, SOI structures (both frilly-depleted and partially-depleted structures) are not infallible. SOI structures suffer particularly from free floating body effects (“FBE”).
An SOI transistor structure has several material interface areas containing dangling bonds or broken bonds resulting in trap sites. Trap sites are created by incomplete bonded species. Typical trap sites can exist at a gate electrode/gate oxide interface, within the bulk oxide film, and the oxide film/substrate interface. Trap sites are normally uncharged but can become charged regions when electrons and holes are introduced into the oxide and become trapped at a site. For instance, highly energetic electrons or holes present in the oxides can charge trap sites. These highly energetic electrons and holes are called hot carriers.
In essence, semiconductor devices have many electrons present in the valence band. When a highly energetic electron in the conduction band undergoes a collision with another electron in the valence band, an electron-hole pair is created. This process is called impact ionization. Once hot carriers (i.e., energetic electrons or holes) are present in the conduction band, they undesirably contribute to the overall conduction current. For instance, the high electric field present in the drain region can produce such hot carriers. The hot carriers generated become trapped at the trap sites and add an electrical charge contributing to the overall fixed charge of the gate oxide; thus, changing the threshold voltage and operating characteristics of the transistor. Unlike non-SOI devices, SOI devices do not have a body (substrate) contact. Because of the lack of this substrate contact, charges are trapped and can accumulate in the SOI substrate. The presence of accumulated extra charge can lead to the device becoming uncontrollable, creating a “floating body effect” (“FBE”) since there is no electrical path to pull the charges off as might be present in a conventional CMOS device. Also, in comparison to CMOS devices, SOI devices have additional traps sites present on the interface with the BOX layer (buried oxide layer). For instance, in fully-depleted SOI devices, the source and drain regions terminate at the BOX layer. Therefore, in the BOX layer, a substrate region is present that is completely confined by SiO2, BOX, and the source and drain, which confines charges at the trap sites.
Ideally, a semiconductor device's gate potential would have complete control over the device's switching characteristics. However, the presence of trapped charges in between the valence band and conduction band, i.e., the forbidden gap, does not allow the gate potential to have complete control. For instance, in NMOS devices, trapped electron charges increase the gate threshold (Vt) thereby decreasing the transconductance and saturation current.
A conventional method of reducing the density of trap sites is by passivating the trap sites with a passivation species at the very end of the fabrication process flow. This passivation step is also called the alloy step or low temperature anneal step (below 500° C.). Ideally, a passivating species occupies and complexes with the trap site making the trap sites resistant to becoming charged.
However, hot carriers, i.e., highly energetic electrons, can displace the passivating species from trap sites. Hot carriers arise through device operation, subsequent processing operations such as plasma processes; and when the oxide film is exposed to radiation environments (i.e., PECVD, sputtering, and ion implantation). As mentioned previously, hot carriers can arise during device operation when electric fields are created by applying voltages across the entire device. As a result, hot carriers decrease the lifetime and reliability of the semiconductor device. Reducing the number of trap sites with a passivation species that is resistant to hot carriers, would greatly enhance the reliability of the device and especially in SOI devices, reduce the FBE normally observed.
One such passivating species utilized is hydrogen. Recently however, deuterium has been shown to be a far superior passivating species than hydrogen by a factor of 30. Cheng et al., Improved Hot-Carrier Reliability of SOI Transistors by Deuterium Passivation of Defects at Oxide/Silicon Interfaces, IEEE Transactions on Electron Devices, Vol. 49., No. 3, March 2002, pgs. 529-531. In essence, deuterium is an isotope of hydrogen and possesses a larger molecular size and is less susceptible than hydrogen to being displaced by hot carriers. However, there are limitations in the effectiveness of deuterium passivation utilizing current methods since deuterium does not easily replace nor displace the hydrogen that already occupies some trap sites.
There are many sources of hydrogen during normal integrated circuit fabrication. Any anneal step such as diffusion or oxidation are potential sources of hydrogen. As a result, it is likely that most of the dangling bonds are already passivated by hydrogen prior to a deuterium anneal process. For a deuterium anneal to be effective, it is important to remove these hydrogen complexed bonds as much as possible. Furthermore, removing hydrogen from a passivated trap site requires energy. Current methods of deuterium passivation yield only a marginal one to two percent improvement of device reliability.
The passivation of a silicon dangling bond by hydrogen requires an activation energy of 1.51 eV (Si−+H2=Si—H+H). Passivation of a silicon dangling bond by deuterium requires an analogous activation energy of 1.51 eV (Si31 +D2=Si-D+D). Whereas, replacing a hydrogen-passivated bond by deuterium (Si—H+D2=Si-D+HD) requires an activation energy of 1.84 eV. As a result, deuterium incorporation at the silicon/oxide interface is largely limited by the replacement of pre-existing hydrogen with deuterium. Therefore, an efficient method is needed to remove the existing hydrogen from passivated sites prior to the deuterium passivation process.
Accordingly, there is a need for an SOI structure with a reduced fixed oxide charge, lower density of trap sites, and improved resistance to hot carrier effects. There is also a need for an SOI structure that has improved deuterium passivation as a result of a deuterium anneal.